Renesas has introduced a new dual-side-cooled 650V GaN FET designed specifically to address the severe thermal and spatial constraints in 800V AI data center power boards. The innovative cooling approach significantly enhances power density and thermal headroom, enabling more efficient power delivery for high-density AI racks.
Overview of the New Dual-Side-Cooled GaN FET
Renesas Electronics has introduced the TP65H020G4PLSGBD, a 650V gallium nitride (GaN) field-effect transistor (FET) featuring a pioneering dual-side cooling mechanism. Designed explicitly for the rigorous thermal and spatial constraints of 800V AI data center power boards, this device addresses the escalating power demands of modern AI racks. As rack power scales from approximately 120 kW toward the megawatt range, efficient power delivery becomes critical. Samples are currently being distributed to major AI data center original equipment manufacturers (OEMs) and original design manufacturers (ODMs).
Thermal Management and Packaging Innovations
The most significant innovation of the TP65H020G4PLSGBD lies in its thermal architecture. Housed in a compact 8x8 mm PQFN package, the footprint is 57% smaller than the existing 10x15 mm TOLT package. Unlike conventional top-side-cooled components that dissipate heat in a single direction, this GaN FET releases heat from both the top and bottom surfaces. According to Renesas, this dual-sided approach reduces top-side thermal impedance by 10%. The datasheet specifies a junction-to-case thermal resistance of 0.36 °C/W through the top and 2.8 °C/W through the bottom. Furthermore, the package adheres to an industry-standard footprint, co-defined with major AI infrastructure customers, ensuring multi-vendor sourcing flexibility.
Architectural Design and Electrical Specifications
Built on the Gen IV Plus platform, the device integrates a high-voltage depletion-mode GaN high-electron-mobility transistor (HEMT) with a low-voltage silicon MOSFET. This configuration delivers the high switching speeds of GaN while ensuring normally-off operation and compatibility with standard silicon gate drivers, requiring no negative gate bias. Key electrical specifications include a typical threshold voltage of 4V, a recommended 9V on-state drive, and a typical on-resistance of 20 mΩ (25 mΩ maximum). The continuous drain current reaches 92 A at a 25°C case temperature, with a junction operating range of -55°C to +150°C. Additionally, the typical gate charge is 19.6 nC, output charge is 221 nC, and the built-in freewheeling diode exhibits negligible reverse recovery charge, facilitating MHz switching and reducing passive component sizes. The device blocks 650V and tolerates transient excursions up to 900V for under 10 µs.
Market Context: The 800V AI Data Center Shift
The introduction of this GaN FET aligns with a broader industry transition toward 800V high-voltage direct current (HVDC) distribution schemes in data centers. AI racks are consuming power at an unprecedented rate, quickly exhausting available physical space and thermal headroom on power distribution boards before reaching electrical limits. By targeting the 800V DC/DC intermediate bus converter stages—which step down voltage to 48V, 12V, or 6V—and sidecar power rack battery backup and capacitor bank (CBU) stages, Renesas is positioning this component at the heart of next-generation power architectures. The company also highlights applications in telecom power supplies, photovoltaic inverters, uninterruptible power supplies, e-mobility charging, and battery energy storage systems.
Implications for Power Density and System Design
To validate the performance of the new device, Renesas developed a 6 kW, 800V-to-48V LLC DC transformer reference design controlled by an RA6T3 MCU. This design achieves a remarkable power density of 2.6 kW/in³. Per-module testing demonstrated a full-load efficiency improvement of 0.21% compared to an equivalent board utilizing the larger TOLT package. Beyond efficiency, the reduced package size significantly saves printed circuit board (PCB) space and enables a more optimized layout across multiple FETs. By pairing the GaN FET with Renesas auxiliary controllers, gate drivers, and microcontrollers, the company offers a comprehensive, single-vendor solution for engineering teams transitioning to 800V platforms.
Future Outlook and Production Roadmap
The TP65H020G4PLSGBD represents a strategic trade-off, replacing a larger, one-sided thermal path with a smaller, highly efficient two-sided thermal solution, all while maintaining compatibility with existing silicon gate driver ecosystems. Renesas is scheduled to showcase the device at the OCP Global Summit in San Jose from October 12 to 15, 2026. Following the current sampling phase with key OEMs and ODMs, mass production is officially slated for mid-2027. As high-voltage converter designers grapple with escalating density and thermal challenges across various high-power sectors, the successful production ramp of this dual-side-cooled GaN FET will be a critical milestone for the power electronics industry.